Pixie Specification - Version 1.0

Table of Contents

1 Introduction

Pixie is an abstract computer. This document describes the features and architecture of Pixie.

2 Instruction Set Architecture

The following sections define the instruction set architecture of Pixie.

2.1 Notation

The notation defined in this section will be used throughout this document.

Table 1: Notation
Notation Description
X[l:r] The field delimited by bit l on the left and r on the right (both inclusive) of the element X.
X[b] Same as X[b:b].
MemB[addr] Refers to the 8-bit memory location at address addr.
MemS[addr] Refers to the 16-bit memory location at address addr.
MemW[addr] Refers to the 32-bit memory location at address addr.
Port[p] Refers to the contents of I/O port numbered p.
LShift(X, n) Shift X to the left by n bits and zero-fill the vacated bit positions.
RShift(X, n) Shift X to the right by n bits and zero-fill the vacated bit positions.
RAShift(X, n) Shift X to the right by n bits. Sign-extend the vacated bit positions.
ZExtend(X, n) Zeroes are appended to the left of X to make it n bits wide.
SExtend(X, n) Replicate the most significant bit of X as many times as necessary to make it n bits wide.
SCT[n] The nth entry in the system call table.
Set_Flags(X) Update ZF, PF, and NF according to the value X.
Next_Reg(n) The general purpose register numbered (n + 1) modulo 8.

2.2 Memory Address Space

Pixie can address 220 memory locations each containing a byte. Addresses are numbered from 0x00000 to 0xfffff. Some regions of memory are reserved for special uses as mentioned in Memory Layout.

2.3 Data Types

The basic data types of Pixie are bytes (8 bits), shorts (16 bits), words (32 bits), and doublewords (64 bits). A byte can be located at any memory location. Shorts, words, and doublewords must be aligned in memory at natural boundaries. That is, a short must be located at an even-numbered address, a word must be located at an address divisible by four, and a doubleword must be located at an address divisible by eight. Unaligned memory accesses will result in an error that will be handled in an implementation-defined manner.

Some instructions interpret these basic data types as signed and unsigned integers or addresses.

2.4 Endianness and Addressing

Bits of a memory location are arranged from right to left such that the least significant bit is in the rightmost position and most significant bit is in the leftmost position.

Shorts and words are stored in memory such that the least significant byte is stored at the smallest memory address. The address of a short or word is the address of its least significant byte.

2.5 Modes of Operation

At any point of time, Pixie operates in one of the two modes - user mode or supervisor mode. The user mode is used to run normal programs while the supervisor mode is used by the operating system and interrupt handlers. Certain privileged instructions are only allowed in the supervisor mode.

The current mode is indicated by the Mode Indicator Bit in the machine status register. This bit can only be changed using a mode switching operation.

2.6 Mode Switching

The processor switches from user mode to supervisor mode on any of the following conditions:

  • When an interrupt is serviced as described in Interrupt Handling section.
  • When the processor executes the SCL instruction.

The processor switches from supervisor mode to user mode on any of the following conditions:

  • When the processor executes the RETI instruction and the Mode Indicator bit in the machine status register image in the stack is clear.
  • When the processor executes the RETS instruction.

2.7 Registers

2.7.1 General Purpose Registers

There are 32 general purpose registers numbered from 0 to 31 which are 32-bits wide. The assembly instructions refer to these registers as R0 to R31 respectively.

2.7.2 Stack Pointer

The general purpose register R15 is used as a stack pointer by some instructions.

2.7.3 Program Counter Register

There is a 20-bit program counter register - named PC - that contains the address of the next instruction to be processed. The address stored in this register must be word aligned.

2.7.4 Machine Status Register

There is an 32-bit machine status register - named MS - that contains various flags to indicate the status of the processor. The flags are:

Table 2: Machine Status Register
Bit Position Description
0 Zero Flag (ZF). This bit is set when the result of an operation is zero.
1 Positive Flag (PF). This bit is set when result of an operation is positive.
2 Negative Flag (NF). This bit is set when result of an operation is negative.
3-15 Reserved.
16 Mode Indicator (MI). This bit is set when the processor is in supervisor mode.
17-31 Reserved.

The machine status register cannot be loaded or stored directly by instructions but accessed only indirectly.

2.7.5 Supervisor Stack Pointer Register

There is a 20-bit supervisor stack pointer register - named SSP - that contains the address of a stack to be used in supervisor mode.

2.8 Memory Layout

Memory address space of Pixie is classified as shown below.

Table 3: Memory Layout
Start Address End Address Description
0x00000 0x000ff Interrupt Vector Table (IVT)
0x00100 0x001ff System Call Table (SCT)
0x00200 0x07fff Operating System
0x08000 0xfffff Available for user programs

The address space below 0x08000 is called protected address space. It is and error to access the protected address space while in user mode and such accesses will be handled in an implementation-defined manner.

2.9 CPU Operation

Much like any conventional CPU, Pixie executes programs by executing instructions in an instruction cycle. Each cycle consists of the following steps in order:

  1. Handle any pending interrupts as mentioned in Interrupt Handling section.
  2. Fetch the instruction addressed by the program counter register.
  3. Increment program counter register by 4.
  4. Decode the instruction. Any indirect memory contents required by the instruction are fetched during this step.
  5. Execute the instruction.

2.10 Input and Output

2.10.1 I/O Address Space

The I/O address space consists of 256 independently addressable 32-bit ports. These ports are numbered from 0 to 255. The I/O address space is separate from the memory address space. It can only be accessed by privileged instructions executed in supervisor mode.

2.10.2 Interrupt Handling

An interrupt is an asynchronous event triggered by an I/O device. An interrupt is identified with a number, called an interrupt vector. Pixie supports 64 interrupt vectors numbered from 0 to 63.

The processor checks for pending interrupts before beginning execution of every instruction. If an interrupt is pending, the processor performs the following operations to service the interrupt:

  1. Check IVT entry corresponding to the interrupt vector. If the entry indicates that the interrupt is disabled, no further processing is done. Otherwise, the following steps are performed.
  2. If the processor is in user mode, load ZExtend(SSP, 32) to R15 and push the old value of R15 to this new stack.
  3. Push MS and PC to the stack in that order.
  4. The Mode Indicator bit in the machine status register is set to indicate that the processor is now executing in supervisor mode.
  5. Load the address of the interrupt handler routine from the IVT entry to PC.
  6. Processor begins execution of the interrupt handler routine.

The interrupt handler routine can execute the RETI instruction to transfer the control back to the point where the interrupt occurred.

2.10.3 Interrupt Vector Table

The interrupt vector table (IVT) is a data structure located at memory address 0x00000. It is an array of 64 elements corresponding to each of the interrupt vectors. Each element of IVT is word sized and has the following structure:

Table 4: IVT Entry Format
Bit Position Description
0-19 Address of the interrupt handler routine
20-30 Reserved. Must be set to zero by the operating system.
31 Interrupt Enable Bit. The interrupt is ignored if this bit clear.

The operating system is responsible for populating entries in this table during initialization.

2.11 System Calls

User mode programs can invoke services provided by the operating system using the SCL instruction. This instruction provides a protected way of transferring control from user mode to supervisor mode.

A system call is identified by a number called the system call vector. A total of 64 system call vectors are supported numbered from 0 to 63.

Upon encountering the SCL instruction, the processor performs the following steps:

  1. Check the SCT entry corresponding to the system call vector. Disabled entries will result in an error which will be handled in an implementation-defined manner.
  2. Load ZExtend(SSP, 32) to R15 and push the old value of R15 in this new stack.
  3. Push MS and PC to the stack in that order.
  4. The Mode Indicator bit in the machine status register is set to indicate that the processor is now executing in supervisor mode.
  5. Load the address of the system call handler routine from the SCT entry to PC.
  6. Processor begins execution of the system call handler routine.

Additional parameters can be passed to the system call handler routine in the general purpose registers or user mode stack.

The system call handler routine can return to user mode by executing the RETS instruction. Results can be passed to user mode caller in the general purpose registers or user mode stack.

2.11.1 System Call Table

The system call table (SCT) is a data structure located at memory address 0x00100. It is an array of 64 elements corresponding to each of the system call vectors. Each element of SCT is word sized and has the following structure:

Table 5: SCT Entry Format
Bit Position Description
0-19 Address of the system call handler routine
20-30 Reserved. Must be set to zero by the operating system.
31 System Call Enable Bit. The system call fails if this bit is clear.

The operating system is responsible for populating entries in this table during initialization.

2.12 Initialization

During start up, Pixie is initialized to the following state:

Table 6: System Initial State
Element Initial State
General Purpose Registers 0x00000000
Program Counter Register 0x00200
Machine Status Register 0x00010001
Supervisor Stack Pointer Register 0x00000
IVT All entries are set to 0x00000000.
SCT All entries are set to 0x00000000.
Memory Contents of memory locations other than IVT and SCT are undefined.

An implementation of Pixie may load an operating system and user program(s) into memory during startup in an implementation-defined manner.

2.13 Instruction Format

An instruction is comprises of an opcode, an optional destination operand, zero to two source operands arranged in that order.

The operands are classified into different categories mentioned below.

2.13.1 Register Operands

These operands are located in a general purpose register. They are denoted as SR and DR in the instructions. They are encoded by their 5 bit register numbers.

2.13.2 Immediate Operands

These operands are located in the instruction itself. They are denoted as imm5, imm6, imm8, and imm16 in the instructions and have lengths of 5, 6, 8, and 16 bits respectively. They are encoded by 5 bit, 6 bit, 8 bit, or 16 bit numbers respectively.

2.13.3 Absolute Address Operands

These operands are memory addressed located in the instruction itself. They are denoted as addr20 in the instructions and have a length of 20 bits. They are encoded as a 20 bit number.

2.13.4 Register Indirect

These operands are located in a memory location whose address is located in a general purpose register. They are denoted as [SR] and [DR] in the instructions. They are encoded by their 5 bit register numbers.

2.13.5 Register Indirect with Index Register

These operands are located in a memory location whose address is formed by adding the contents of two general purpose registers. They are denoted as [SR1+SR2] or [DR1+DR2] in the instructions. They are encoded by two 5 bit register numbers arranged consecutively.

3 Instructions

This section contains a comprehencive list of all instructions and their encodings.

Many instruction encodings contain bit fields marked as Reserved. These must be filled with zeroes for compatibility reasons.

3.1 ADD

Adds two source operands and stores the result in the destination operand.

3.1.1 Encodings

Table 7: ADD DR, SR1, SR2
Bit Position 31-27 26-22 21-17 16 15-5 4-0
  0b00100 DR SR1 0 Reserved SR2
Table 8: ADD DR, SR1, imm16
Bit Position 31-27 26-22 21-17 16 15-0
  0b00100 DR SR1 1 imm16

3.1.2 Operation

if (instruction[16] == 0)
  DR = SR1 + SR2;
else
  DR = SR1 + SExtend(imm16, 32);

Set_Flags(DR);

3.1.3 Flags Affected

ZF, PF, NF

3.2 SUB

Subtracts the second source operand from the first source operand and stores the result in the destination operand.

3.2.1 Encodings

Table 9: SUB DR, SR1, SR2
Bit Position 31-27 26-22 21-17 16 15-5 4-0
  0b00000 DR SR1 0 Reserved SR2
Table 10: SUB DR, SR1, imm16
Bit Position 31-27 26-22 21-17 16 15-0
  0b00000 DR SR1 1 imm16

3.2.2 Operation

if (instruction[16] == 0)
  DR = SR1 - SR2;
else
  DR = SR1 - SExtend(imm16, 32);

Set_Flags(DR);

3.2.3 Flags Affected

ZF, PF, NF

3.3 MUL

Multiples two source operands and stores the result in the destination operand. The size of the destination operand is always double that of the source operands.

The signed instruction variant (MULBI, MULSI, and MULWI) multiplies two signed numbers and stores the result into the destination operand. The unsigned instruction variant (MULBU, MULSU, and MULWU) multiplies two unsigned numbers and stores the result into the destination operand.

Both these instruction variants are further classified into byte, short, and word variants.

The byte instruction variant multiplies the least significant 8 bits of the source operands and stores the result into the least significant 16 bits of the destination operand.

The short instruction variant multiplies the least significant 16 bits of the source operands and stores the result into the destination operand word.

The word instruction variant multiplies the source operand words and stores the result into the destination operand doubleword. The least significant word of the result is stored in the register DR and the most significant word in the register (DR + 1) modulo 8.

3.3.1 Encodings

Table 11: MULBI DR, SR1, SR2
Bit Position 31-27 26 25-24 23-15 14-10 9-5 4-0
  0b01111 0 0b01 Reserved DR SR1 SR2
Table 12: MULSI DR, SR1, SR2
Bit Position 31-27 26 25-24 23-15 14-10 9-5 4-0
  0b01111 0 0b10 Reserved DR SR1 SR2
Table 13: MULWI DR, SR1, SR2
Bit Position 31-27 26 25-24 23-15 14-10 9-5 4-0
  0b01111 0 0b11 Reserved DR SR1 SR2
Table 14: MULBU DR, SR1, SR2
Bit Position 31-27 26 25-24 23-15 14-10 9-5 4-0
  0b01111 1 0b01 Reserved DR SR1 SR2
Table 15: MULSU DR, SR1, SR2
Bit Position 31-27 26 25-24 23-15 14-10 9-5 4-0
  0b01111 1 0b10 Reserved DR SR1 SR2
Table 16: MULWU DR, SR1, SR2
Bit Position 31-27 26 25-24 23-15 14-10 9-5 4-0
  0b01111 1 0b11 Reserved DR SR1 SR2

3.3.2 Operation

if (instruction[25:24] == 1) {
  op1 = SR1[7:0];
  op2 = SR2[7:0];
} else if (instruction[25:24] == 2) {
  op1 = SR1[15:0];
  op2 = SR2[15:0];
} else if (instruction[25:24] == 3) {
  op1 = SR1;
  op2 = SR2;
}

if (instruction[26] == 0)
  result = Signed_Multiply(op1, op2);
else
  result = Unsigned_Multiply(op1, op2);

if (instruction[25:24] == 1)
  DR[15:0] = result;
else if (instruction[25:24] == 2)
  DR = result;
else if (instruction[25:24] == 3) {
  DR = result[31:0];
  Next_Reg(DR) = result[63:32];
}

Set_Flags(result);

3.3.3 Flags Affected

ZF, PF, NF

3.4 NEG

Two's complement negation.

Sets the destination operand to the two's complement of the source operand.

3.4.1 Encodings

Table 17: NEG DR, SR
Bit Position 31-27 26-10 9-5 4-0
  0b11000 Reserved DR SR

3.4.2 Operation

DR = -SR;

Set_Flags(DR);

3.4.3 Flags Affected

ZF, PF, NF

3.5 CMP

Compares two operands.

The comparison is perdformed by subtracting the second source operand from the first source operand and setting the flags according to the result. The result is discarded.

3.5.1 Encodings

Table 18: CMP SR1, SR2
Bit Position 31-27 26-22 21-17 16 4-0
  0b11011 Reserved SR1 0 SR2
Table 19: CMP SR1, imm16
Bit Position 31-27 26-22 21-17 16 15-0
  0b11011 Reserved SR1 1 imm16

3.5.2 Operation

if (instruction[16] == 0)
  result = SR1 - SR2;
else
  result = SR1 - SExtend(imm16, 32);

Set_Flags(result);

3.5.3 Flags Affected

ZF, PF, NF

3.6 AND

Performs bitwise logical AND of two source operands and stores the result in the destination operand.

3.6.1 Encodings

Table 20: AND DR, SR1, SR2
Bit Position 31-27 26-22 21-17 16 15-5 4-0
  0b00101 DR SR1 0 Reserved SR2
Table 21: AND DR, SR1, imm16
Bit Position 31-27 26-22 21-17 16 15-0
  0b00101 DR SR1 1 imm16

3.6.2 Operation

if (instruction[16] == 0)
  DR = SR1 && SR2
else
  DR = SR1 && SExtend(imm16, 32)

Set_Flags(DR);

3.6.3 Flags Affected

ZF, PF, NF

3.7 OR

Performs bitwise logical OR of two source operands and stores the result in the destination operand.

3.7.1 Encodings

Table 22: OR DR, SR1, SR2
Bit Position 31-27 26-22 21-17 16 15-5 4-0
  0b01101 DR SR1 0 Reserved SR2
Table 23: OR DR, SR1, imm16
Bit Position 31-27 26-22 21-17 16 15-0
  0b01101 DR SR1 1 imm16

3.7.2 Operation

if (instruction[16] == 0)
  DR = SR1 || SR2
else
  DR = SR1 || SExtend(imm16, 32)

Set_Flags(DR);

3.7.3 Flags Affected

ZF, PF, NF

3.8 NOT

Bitwise complement.

Perform a bitwise complement of the source operand and store the result into the destination operand.

3.8.1 Encodings

Table 24: NOT DR, SR
Bit Position 31-27 26-10 9-5 4-0
  0b10110 Reserved DR SR

3.8.2 Operation

DR = ~SR;

Set_Flags(DR);

3.8.3 Flags Affected

ZF, PF, NF

3.9 XOR

Bitwise exclusive-OR.

3.9.1 Encodings

Table 25: XOR DR, SR1, SR2
Bit Position 31-27 26-22 21-17 16 15-5 4-0
  0b10101 DR SR1 0 Reserved SR2
Table 26: XOR DR, SR1, imm16
Bit Position 31-27 26-22 21-17 16 15-0
  0b10101 DR SR1 1 imm16

3.9.2 Operation

if (instruction[16] == 0)
  DR = SR1 ^ SR2
else
  DR = SR1 ^ SExtend(imm16, 32)

Set_Flags(DR);

3.9.3 Flags Affected

ZF, PF, NF

3.10 SHF

Bit shift.

Shift the source operand by a specified number of bits to the left or right and store the result in the destination operand.

The left shift operation (SHFL) fills the vacated bit positions with zeroes. The right shift operation can be logical or arithmetic. The logical right shift operation (SHFRZ) fills the vacated bit positions with zeroes while the arithmetic right shift operation (SHFRA) fills the vacated bit positions by the most significant bit.

3.10.1 Encodings

Table 27: SHFL DR, SR1, SR2
Bit Position 31-27 26-25 24-16 15-11 10-6 5 4-0
  0b10000 0b00 Reserved DR SR1 0 SR2
Table 28: SHFL DR, SR, imm5
Bit Position 31-27 26-25 24-16 15-11 10-6 5 4-0
  0b10000 0b00 Reserved DR SR 1 imm5
Table 29: SHFRZ DR, SR1, SR2
Bit Position 31-27 26-25 24-16 15-11 10-6 5 4-0
  0b10000 0b10 Reserved DR SR1 0 SR2
Table 30: SHFRZ DR, SR, imm5
Bit Position 31-27 26-25 24-16 15-11 10-6 5 4-0
  0b10000 0b10 Reserved DR SR 1 imm5
Table 31: SHFRA DR, SR1, SR2
Bit Position 31-27 26-25 24-16 15-11 10-6 5 4-0
  0b10000 0b11 Reserved DR SR1 0 SR2
Table 32: SHFRA DR, SR, imm5
Bit Position 31-27 26-25 24-16 15-11 10-6 5 4-0
  0b10000 0b11 Reserved DR SR 1 imm5

3.10.2 Operation

if (instruction[5] == 0) {
  op = SR1;
  count = SR2;
} else {
  op = SR;
  count = imm5;
}

if (instruction[26:25] == 0)
  DR = LShift(op, count);
else if (instruction[26:25] == 2)
  DR = RShift(op, count);
else if (instruction[26:25] == 3)
  DR = RAShift(op, count);

Set_Flags(DR);

3.10.3 Flags Affected

ZF, PF, NF

3.11 JC

Jump conditionally. Tests zero or more flags and performs a jump if any of them are set.

Note that JCnzp will always perform a jump regardless of the state of the flags and JC will never perform the jump. For this reason, it is not necessary for assemblers to support these instruction variants.

It is an error if the target address of the jump is not word aligned.

3.11.1 Encodings

  • JC addr20
  • JCn addr20
  • JCp addr20
  • JCz addr20
  • JCnp addr20
  • JCnz addr20
  • JCzp addr20
  • JCnzp addr20
Table 33: JC addr20
Bit Position 31-27 26 25 24 23-22 21-20 19-0
  0b10111 n p z Reserved 0b00 addr20
  • JC [SR]
  • JCn [SR]
  • JCp [SR]
  • JCz [SR]
  • JCnp [SR]
  • JCnz [SR]
  • JCzp [SR]
  • JCnzp [SR]
Table 34: JC [SR]
Bit Position 31-27 26 25 24 23-22 21-20 19-5 4-0
  0b10111 n p z Reserved 0b01 Reserved [SR]
  • JC [SR1+SR2]
  • JCn [SR1+SR2]
  • JCp [SR1+SR2]
  • JCz [SR1+SR2]
  • JCnp [SR1+SR2]
  • JCnz [SR1+SR2]
  • JCzp [SR1+SR2]
  • JCnzp [SR1+SR2]
Table 35: JC [SR1+SR2]
Bit Position 31-27 26 25 24 23-22 21-20 19-10 9-5 4-0
  0b10111 n p z Reserved 0b10 Reserved SR1 SR2

3.11.2 Operation

if ((n && NF) || (p && PF) || (z && ZF)) {
  if (instruction[21:20] == 0)
    addr = addr20;
  else if (instruction[21:20] == 1)
    addr = SR[19:0];
  else if (instruction[21:20] == 2)
    addr = (SR1 + SR2)[19:0];

  if ((addr % 4) != 0)
    Handle alignment error;
  else
    PC = addr;
}

3.11.3 Flags Affected

None.

3.12 JMP

Jump unconditionally.

Note that this instruction uses the same opcode as JC and the encoding is the same as JCnzp.

It is an error if the target address of the jump is not word aligned.

3.12.1 Encodings

Table 36: JMP addr20
Bit Position 31-27 26-24 23-22 21-20 19-0
  0b10111 0b111 Reserved 0b00 addr20
Table 37: JMP [SR]
Bit Position 31-27 26-24 23-22 21-20 19-5 4-0
  0b10111 0b111 Reserved 0b01 Reserved SR
Table 38: JMP [SR1+SR2]
Bit Position 31-27 26-24 23-22 21-20 19-10 9-5 4-0
  0b10111 0b111 Reserved 0b10 Reserved SR1 SR2

3.12.2 Operation

if (instruction[21:20] == 0)
  addr = addr20;
else if (instruction[21:20] == 1)
  addr = SR[19:0];
else if (instruction[21:20] == 2)
  addr = (SR1 + SR2)[19:0];

if ((addr % 4) != 0)
  Handle alignment error;
else
  PC = addr;

3.12.3 Flags Affected

None.

3.13 CALL

Call subroutine.

Saves return information on the stack and branches to the called subroutine.

It is an error if the address of the subroutine is not word aligned.

3.13.1 Encodings

Table 39: CALL addr20
Bit Position 31-27 26 25-22 21-20 19-0
  0b01000 0 Reserved 0b00 addr20
Table 40: CALL [SR]
Bit Position 31-27 26 25-22 21-20 19-5 4-0
  0b01000 0 Reserved 0b01 Reserved SR
Table 41: CALL [SR1+SR2]
Bit Position 31-27 26 25-22 21-20 19-10 9-5 4-0
  0b01000 0 Reserved 0b10 Reserved SR1 SR2

3.13.2 Operation

R15 = R15 - 4;
MemW[R15] = ZExtend(PC, 32);
if (instruction[21:20] == 0)
  addr = addr20;
else if (instruction[21:20] == 1)
  addr = SR[19:0];
else if (instruction[21:20] == 2)
  addr = (SR1 + SR2)[19:0];

if ((addr % 4) != 0)
  Handle alignment error;
else
  PC = addr;

3.13.3 Flags Affected

None.

3.14 SCL

Call operating system service.

Saves return information on the stack and branches to a system call handler routine.

It is an error if the address of the system call handler routine is not word aligned.

3.14.1 Encodings

Table 42: SCL imm6
Bit Position 31-27 26 25-6 5-0
  0b01000 1 Reserved imm6

3.14.2 Operation

if (SCT[imm6][31] == 0)
  Handle SCT disabled error;
else {
  temp = R15;
  R15 = ZExtend(SSP, 32);
  R15 = R15 - 4;
  MemW[R15] = temp;
  R15 = R15 - 4;
  MemW[R15] = MS;
  R15 = R15 - 4;
  MemW[R15] = ZExtend(PC, 32);
  MI = 1;

  addr = SCT[imm6][19:0];
  if ((addr % 4) != 0)
    Handle alignment error;
  else
    PC = addr;
}

3.14.3 Flags Affected

MI

3.15 RET

Return from a subroutine, interrupt handler routine, or a system call handler routine.

Restores the return information from the stack and branches to the caller or savepoint.

It is an error if the target address of the return is not word aligned.

3.15.1 Encodings

Table 43: RET
Bit Position 31-27 26 25-0
  0b00011 0 Reserved
Table 44: RETI or RETS
Bit Position 31-27 26 25-0
  0b00011 1 Reserved

3.15.2 Operation

if (instruction[26] == 1 && MI == 0)
  Handle privilege violation error;

addr = MemW[R15][19:0];
R15 = R15 + 4;

if ((addr % 4) != 0)
  Handle alignment error;
else {
  PC = addr;

  if (instruction[26] == 1) {
    MS = MemW[R15];
    R15 = R15 + 4;
    if (MI == 0) {
      R15 = MemW[R15];
    }
  }
}

3.15.3 Flags Affected

ZF, PF, NF, MI

3.16 LD

Load a byte, short, or word from memory to a register.

The source operand specifies a memory address. The contents of this address is optionally sign extended and stored into the destination register.

3.16.1 Encodings

Table 45: LDB DR, addr20
Bit Position 31-27 26-22 21-20 19-0
  0b01001 DR 0b00 addr20
Table 46: LDB DR, [SR]
Bit Position 31-27 26-22 21-20 19-5 4-0
  0b01001 DR 0b01 Reserved SR
Table 47: LDB DR, [SR1+SR2]
Bit Position 31-27 26-22 21-20 19-10 9-5 4-0
  0b01001 DR 0b10 Reserved SR1 SR2
Table 48: LDS DR, addr20
Bit Position 31-27 26-22 21-20 19-0
  0b01010 DR 0b00 addr20
Table 49: LDS DR, [SR]
Bit Position 31-27 26-22 21-20 19-5 4-0
  0b01010 DR 0b01 Reserved SR
Table 50: LDS DR, [SR1+SR2]
Bit Position 31-27 26-22 21-20 19-10 9-5 4-0
  0b01010 DR 0b10 Reserved SR1 SR2
Table 51: LDW DR, addr20
Bit Position 31-27 26-22 21-20 19-0
  0b01011 DR 0b00 addr20
Table 52: LDW DR, [SR]
Bit Position 31-27 26-22 21-20 19-5 4-0
  0b01011 DR 0b01 Reserved SR
Table 53: LDW DR, [SR1+SR2]
Bit Position 31-27 26-22 21-20 19-10 9-5 4-0
  0b01011 DR 0b10 Reserved SR1 SR2

3.16.2 Operation

if (instruction[21:20] == 0)
  addr = addr20;
else if (instruction[21:20] == 1)
  addr = SR[19:0];
else if (instruction[21:20] == 2)
  addr = (SR1 + SR2)[19:0];

if (instruction[28:27] == 0)
  DR = SExtend(MemB[addr], 32);
else if (instruction[28:27] == 1)
  DR = SExtend(MemS[addr], 32);
else if (instruction[28:27] == 2)
  DR = MemW[addr];

Set_Flags(DR);

3.16.3 Flags Affected

ZF, PF, NF

3.17 ST

Store a byte, short, or word from a register to memory.

The destination operand specifies a memory address. The least significant 8, 16, or 32 bits of the source register are selected depending on whether the variant of the instruction is STB, STS, or STW respectively. This selected bits are stored at the destination address.

3.17.1 Encodings

Table 54: STB addr20, SR
Bit Position 31-27 26-25 24-5 4-0
  0b11100 0b00 addr20 SR
Table 55: STB [DR], SR
Bit Position 31-27 26-25 24-10 9-5 4-0
  0b11100 0b01 Reserved DR SR
Table 56: STB [DR1+DR2], SR
Bit Position 31-27 26-25 24-15 14-10 9-5 4-0
  0b11100 0b10 Reserved DR1 DR2 SR
Table 57: STS addr20, SR
Bit Position 31-27 26-25 24-5 4-0
  0b11101 0b00 addr20 SR
Table 58: STS [DR], SR
Bit Position 31-27 26-25 24-10 9-5 4-0
  0b11101 0b01 Reserved DR SR
Table 59: STS [DR1+DR2], SR
Bit Position 31-27 26-25 24-15 14-10 9-5 4-0
  0b11101 0b10 Reserved DR1 DR2 SR
Table 60: STW addr20, SR
Bit Position 31-27 26-25 24-5 4-0
  0b11110 0b00 addr20 SR
Table 61: STW [DR], SR
Bit Position 31-27 26-25 24-10 9-5 4-0
  0b11110 0b01 Reserved DR SR
Table 62: STW [DR1+DR2], SR
Bit Position 31-27 26-25 24-15 14-10 9-5 4-0
  0b11110 0b10 Reserved DR1 DR2 SR

3.17.2 Operation

if (instruction[26:25] == 0)
  addr = addr20;
else if (instruction[26:25] == 1)
  addr = DR[19:0];
else if (instruction[26:25] == 2)
  addr = (DR1 + DR2)[19:0];

if (instruction[28:27] == 1)
  MemB[addr] = SR[7:0];
else if (instruction[28:27] == 2)
  MemS[addr] = SR[15:0];
else if (instruction[28:27] == 3)
  MemW[addr] = SR;

3.17.3 Flags Affected

None.

3.18 CPY

Copy a source register or immediate value to the destination register.

The copy instruction has two variants in case of an immediate operand. The value is either sign extended to 32 bits and copied (CPYI) or zero extended to 32 bits and copied (CPYU).

3.18.1 Encodings

Table 63: CPY DR, SR
Bit Position 31-27 26-22 21-17 17-16 15-5 4-0
  0b00010 Reserved DR 0b00 Reserved SR
Table 64: CPYI DR, imm16
Bit Position 31-27 26-22 21-17 17-16 15-0
  0b00010 Reserved DR 0b10 imm16
Table 65: CPYU DR, imm16
Bit Position 31-27 26-22 21-17 17-16 15-0
  0b00010 Reserved DR 0b11 imm16

3.18.2 Operation

if (instruction[17:16] == 0)
  DR = SExtend(imm16, 32);
else if (instruction[17:16] == 1)
  DR = ZExtend(imm16, 32);
else if (instruction[17:16] == 2)
  DR = SR;

3.18.3 Flags Affected

None.

3.19 PUSH

Push the source operand on top of the stack.

The stack pointer (R15) is decremented by 4 and the source operand is stored at that memory location.

There are two variants of the instruction when the source operand is a 16 bit immediate value. The value is either sign extended to 32 bits and copied (PUSHI) or zero extended to 32 bits and copied (PUSHU).

There are three variants of the instruction when the source operand is a register. The value stored in the stack always have a 32 bit size. The value is sign extended to 32 bits if the operand is a byte or short.

3.19.1 Encodings

Table 66: PUSHI imm16
Bit Position 31-27 26 25-24 23-17 16 15-0
  0b11111 0 0b00 Reserved 0 imm16
Table 67: PUSHU imm16
Bit Position 31-27 26 25-24 23-17 16 15-0
  0b11111 0 0b00 Reserved 1 imm16
Table 68: PUSHB SR
Bit Position 31-27 26 25-24 23-5 4-0
  0b11111 0 0b01 Reserved SR
Table 69: PUSHS SR
Bit Position 31-27 26 25-24 23-5 4-0
  0b11111 0 0b10 Reserved SR
Table 70: PUSHW SR
Bit Position 31-27 26 25-24 23-5 4-0
  0b11111 0 0b11 Reserved SR

3.19.2 Operation

R15 = R15 - 4;

if (instruction[25:24] == 0) {
  if (instruction[16] == 0)
    MemW[R15] = SExtend(imm16, 32);
  else
    MemW[R15] = ZExtend(imm16, 32);
} else if (instruction[25:24] == 1) {
  MemW[R15] = SExtend(SR[7:0], 32); 
} else if (instruction[25:24] == 2) {
  MemW[R15] = SExtend(SR[15:0], 32); 
} else if (instruction[25:24] == 3) {
  MemW[R15] = SR;
}

3.19.3 Flags Affected

None.

3.20 POP

Pop the value on the top of the stack to the destination operand.

The 32 bit value stored at the address specified by the stack pointer (R15) is extracted and stored in the destination operand. The stack pointer is incremented by 4 after that.

There are three variants of the instruction - POPB, POPS, and POPW. The POPB variant stores the least significant 8 bits in the destination operand. The POPW variant stores the least significant 16 bits in the destination operand. The POPW variant stores the entire word in the destination operand.

3.20.1 Encodings

Table 71: POPB DR
Bit Position 31-27 26 25-24 23-5 4-0
  0b11111 1 0b01 Reserved DR
Table 72: POPS DR
Bit Position 31-27 26 25-24 23-5 4-0
  0b11111 1 0b10 Reserved DR
Table 73: POPW DR
Bit Position 31-27 26 25-24 23-5 4-0
  0b11111 1 0b11 Reserved DR

3.20.2 Operation

if (instruction[25:24] == 1)
  DR[7:0] = MemB[R15];
else if (instruction[25:24] == 2)
  DR[15:0] = MemS[R15];
else if (instruction[25:24] == 3)
  DR = MemW[R15];


R15 = R15 + 4;

3.20.3 Flags Affected

None.

3.21 IN

Get input from an I/O port.

Extract a word from the I/O port whose number is specified as a source or immediate operand and store it into the destination operand.

This is a privileged instruction and can only be executed in supervisor mode.

3.21.1 Encodings

Table 74: IN DR, SR
Bit Position 31-27 26 25-14 13-9 8 7-5 4-0
  0b01110 0 Reserved DR 0 Reserved SR
Table 75: IN DR, imm8
Bit Position 31-27 26 25-14 13-9 8 7-0
  0b01110 0 Reserved DR 1 imm8

3.21.2 Operation

if (MI == 0)
  Handle privilege violation error;

if (instruction[8] == 0)
  p = SR[7:0];
else
  p = imm8;

DR = Port[p];

Set_Flags(DR);

3.21.3 Flags Affected

ZF, PF, NF

3.22 OUT

Output to an I/O port.

Copy a word from the source operand to an I/O port. The number of the port is mentioned as a destination or immediate operand.

This is a privileged instruction and can only be executed in supervisor mode.

3.22.1 Encodings

Table 76: OUT DR, SR
Bit Position 31-27 26 25-14 13 12-10 9-5 4-0
  0b01110 1 Reserved 0 Reserved DR SR
Table 77: OUT imm8, SR
Bit Position 31-27 26 25-14 13 12-5 4-0
  0b01110 1 Reserved 1 imm8 SR

3.22.2 Operation

if (MI == 0)
  Handle privilege violation error;

if (instruction[13] == 0)
  p = DR[7:0];
else
  p = imm8;

Port[p] = SR;

3.22.3 Flags Affected

None.

3.23 SSSP

Set supervisor stack pointer register.

This is a privileged instruction and can only be executed in supervisor mode.

The value loaded to SSP register must be aligned on a word boundary.

3.23.1 Encodings

Table 78: SSSP addr20
Bit Position 31-27 26-21 20 19-0
  0b00110 Reserved 0 addr20
Table 79: SSSP SR
Bit Position 31-27 26-21 20 19-5 4-0
  0b00110 Reserved 1 Reserved SR

3.23.2 Operation

if (MI == 0)
  Handle privilege violation error;

if (instruction[20] == 0)
  addr = addr20;
else
  addr = SR[19:0];

if ((addr % 4) != 0)
  Handle alignment error;
else
  SSP = addr;

3.23.3 Flags Affected

None.

3.24 HALT

Stop execution and halt the computer.

It is implementation-defined if/how the computer can transition out of the halted state.

This is a privileged instruction and can only be executed in supervisor mode.

3.24.1 Encodings

Table 80: HALT
Bit Position 31-27 26-0
  0b10001 Reserved

3.24.2 Operation

if (MI == 0)
  Handle privilege violation error;
else
  Halt the computer;

3.24.3 Flags Affected

None.

4 Standard I/O Devices

A Pixie implementation must support the following I/O devices.

  • Clock
  • Byte Input
  • Byte Output

4.1 Clock

The clock device can be used to get the current date and time according to the Gregorian calendar. The device does not support updating the date and time. Any additional details related to date and time - such as the timezone or leap second support - are implementation-defined.

The date and time can be read from I/O ports numbered 4 and 5. The words read from these ports have the following format:

Table 81: Date Word (Port 4)
Bit Position 31-25 24-20 19-16 15-0
Description Reserved day month year
Range   1-31 1-12 0-65535
Table 82: Time Word (Port 5)
Bit Position 31-17 16-12 11-6 5-0
Description Reserved hour minute second
Range   0-23 0-59 0-59

4.2 Byte Input

This device provides byte (8-bit) inputs. The device raises interrupt vector 8 when some bytes are available as input.

The interrupt handler routine can read the number of bytes available from I/O port number 8. The word read from this port has the following format.

Table 83: Available Input Byte Count (Port 8)
Bit Position 31-16 15-0
  Undefined Available Byte Count

The handler routine can then read the bytes one by one from I/O port number 9. The word read from this port had the following format.

Table 84: Input Byte (Port 9)
Bit Position 31-8 7-0
  Undefined Input Byte

The count indicated by port 8 decrements by one each time a byte is read from port 9. If a byte is read from port 9 after the count reaches zero, the returned value from port 9 is implementation defined.

4.3 Byte Output

This device can output bytes. The byte should be written to I/O port number 12 for output. The word written to this port must have the following format:

Table 85: Output Byte (Port 12)
Bit Position 31-8 7-0
  Ignored by device Output Byte